1. Field of the Invention
The present invention relates to a filtering apparatus for filtering digital signals, a data driven type information processing apparatus, a filtering method, a filtering program and a machine-readable recording medium having the filtering program recorded thereon. More specifically, the present invention relates to a filtering apparatus for filtering digital signals, a data driven type information processing apparatus, a filtering method, a filtering program and a machine-readable recording medium having the filtering program recorded thereon, for median filtering that removes noise from noisy image data.
2. Description of the Background Art
In image related fields, median filtering process as a method of removing noise from an input image is an important function, an d higher speed of the filtering process is strongly desired.
In the median filtering process, for each pixel of the input image, a window (local area) having the size of K×L with the pixel of interest being at the center is considered, and a central value (median) of luminance data (hereinafter referred to as a pixel value) of K×L pixels is provided as the pixel value of each pixel in of the output image.
Conventionally, in the median filtering process using a 3×3 window, nine pixel values in the window are sorted and the central value of these pixels is calculated.
FIG. 15 shows an exemplary configuration of a conventional median filtering apparatus. The median filtering apparatus shown in FIG. 15 includes sorting circuits 801 to 803, 805, 806, 808, 809 and 811 sorting the input data in ascending or descending order and outputting the result, selectors 804, 807 and 810, maximum value determiners 812 to 814, and minimum value determiners 815 to 817.
An operation of the median filtering apparatus shown in FIG. 15 will be described, taking an example in which a central value of nine pixel values A0 to A2, B0 to B2 and C0 to C2 in a window having the size of 3×3 is calculated.
First, nine pixel values A0 to A2, B0 to B2 and C0 to C2 are divided in advance into three groups G1 to G3 each having three pixel values, and the groups G1 to G3 are input to sorting circuits 801 to 803, respectively.
Sorting circuits 801 to 803 each sorts the three pixel values of the group input thereto and outputs the result of sorting to selector 804. The maximum pixel value represented by the result of sorting is output to maximum value determiner 812, and the minimum value represented by the result of sorting is output to minimum value determiner 815.
Maximum value determiner 812 receives as inputs the maximum pixel values of groups G1 to G3, compares the input pixel values with each other, determines the largest pixel value among the input pixel values, and outputs the result of determination to selector 804. Minimum value determiner 815 receives as inputs the minimum pixel values of groups G1 to G3, compares the input pixel values with each other, determines the smallest pixel value among the input pixel values, and outputs the result of determination to selector 804.
Selector 804 receives as inputs nine pixel values as the result of sorting from sorting circuits 801 to 803, removes therefrom the largest and smallest pixel values represented by the results of determination received from maximum value determiner 812 and minimum value determiner 815, and outputs the result. By this operation, two pixel values are removed from the input nine pixel values, and hence, seven pixel values are output.
Then, selector 804 divides the seven pixel values into three groups having three pixels, three pixels and one pixel, respectively, and outputs these groups. Specifically, the groups consisting of three pixels are output to sorting circuits 805 and 806, respectively, and group 818 consisting of one pixel is output to selector 807, maximum value determiner 813 and minimum value determiner 816. Sorting circuits 805 and 806 sort the pixel values of the input groups respectively, and output the results of sorting to selector 807. The maximum pixel values and the minimum pixel values as represented by the results of sorting are output to maximum value determiner 813 and to minimum value determiner 816, respectively.
Maximum value determiner 813 receives the three pixel values input thereto, compares the input pixel values with each other, determines the largest pixel value among the input pixel values, and outputs the result of determination to selector 807. Minimum value determiner 816 receives the pixel values input thereto, compares the input pixel values with each other, determines the smallest pixel value among the input pixel values, and outputs the result of determination to selector 807.
Selector 807 receives as inputs six pixel values as the result of sorting from sorting circuits 805 and 806 and receives one pixel value of group 818, removes therefrom the largest pixel value and the smallest pixel value represented by the results of determination given from maximum value determiner 813 and minimum value determiner 816, and outputs the result. By this operation, two pixel values are removed from input seven pixel values, and hence, five pixel values are output.
Thereafter, selector 807 divides the five pixel values into a group consisting of three pixel values and a group consisting of two pixel values, and outputs the group consisting of three pixel values to sorting circuit 808 and outputs the group consisting of two pixel values to sorting circuit 809. Sorting circuits 808 and 809 sort the pixel values of the input groups, respectively, output the result of sorting to selector 810, output the maximum pixel values and minimum pixel values as represented by the results of sorting to maximum value determiner 814 and minimum value determiner 817, respectively.
Maximum value determiner 814 compares input pixel values with each other, determines the largest pixel value among the input pixel values, and outputs the result of determination to selector 810. Minimum value determiner 817 compares input pixel values with each other, determines the smallest pixel value among the input pixel values, and outputs the result of determination to selector 810.
Selector 810 receives as inputs five pixel values as the results of sorting from sorting circuits 808 and 809, removes therefrom the largest and smallest pixel values as represented by the results of determination by maximum value determiner 814 and minimum value determiner 817, and outputs the result to sorting circuit 811. By this operation, two pixel values are removed from the input five pixel values, and hence three pixel values are output.
Sorting circuit 811 sorts the three pixel values input from selector 810, and outputs the pixel value at the center of the series of pixel values given as the result of sorting as the median.
In the above described median filtering process, in order to calculate the central value of nine input pixel values, the input pixel values are divided into three groups each consisting of three pixel values and sorting process is performed in each group, and the largest and smallest two pixel values are removed by a selector in accordance with the result of sorting, so as to reduce the number of pixel values as the object of processing. This process is repeated to reduce two by two the number of pixel values as the object of processing, and the central value is eventually obtained. Here, sorting is necessary every time the largest and smallest values are to be removed, and in the example shown in FIG. 15, eight sorting circuits are necessary. Further, three maximum value determiners and three minimum value determiners are necessary. As the sorting circuits, maximum value determiner and minimum value determiner employ comparators, a total of 36 comparators are necessary in the circuitry of FIG. 15 as a whole. Consequently, the circuit scale of the median filtering apparatus becomes large, and the number of pipelines increases when the median filtering process using such a median filtering apparatus is executed along with pipeline processing. Accordingly, it has been difficult to realize high-speed median filtering process.
A filtering apparatus described in Japanese Patent Laying-Open No. 6-61788 includes a register file, which has a plurality of registers and has data, constants and initial values read and written in accordance with the single write and single read rule, and a group of operators having a multiplier and an addition-shift combined operator. Therefore, a basic filtering operation in FIR filtering process and IIR filtering process can be represented as a minimum instruction unit, and the filtering process can be executed at high speed.
Further, the number of entries of the register file corresponds to the number of taps, and therefore, the number of entries can be set by a program, and a filter of an arbitrary configuration can easily be implemented.
This configuration, however, can cope with the FIR and IIR filters only, and only a program-based solution is available to realize the median filtering process.